Integrated on-chip solid state capacitor based on vertically aligned nanofibers, grown using a CMOS temperature compatible process

Com­plete mini­atur­ized on-chip integ­rated sol­id-state capa­cit­ors have been fab­ric­ated based on con­form­al coat­ing of ver­tic­ally aligned car­bon nan­ofibers (VACN­Fs), using a CMOS tem­per­at­ure com­pat­ible micro­fab­ric­a­tion pro­cesses. The 5 µm long VACN­Fs, oper­at­ing as elec­trode, are grown on a sil­ic­on sub­strate and con­form­ally coated by alu­min­um oxide dielec­tric using atom­ic lay­er depos­ition (ALD) tech­nique. The areal (foot­print) capa­cit­ance dens­ity value of 11–15 nF/​mm² is real­ized with high repro­du­cib­il­ity. The CMOS tem­per­at­ure com­pat­ible micro­fab­ric­a­tion, ultra-low pro­file (less than 7 µm thick­ness) and high capa­cit­ance dens­ity would enables dir­ect integ­ra­tion of micro energy stor­age devices on the act­ive CMOS chip, multi-chip pack­age and pass­ives on sil­ic­on or glass inter­poser. A mod­el is developed to cal­cu­late the sur­face area of VACN­Fs and the effect­ive capa­cit­ance from the devices. It is thereby shown that 71 % of sur­face area of the VACN­Fs has con­trib­uted to the meas­ured capa­cit­ance, and by using the entire area the capa­cit­ance can poten­tially be increased.