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CMOS compatible on-chip decoupling capacitor based on vertically aligned carbon nanofibers
Research paper published in Solid–State Electronics, Volume 107, May 2015, pp. 15–19.
One-dimensional carbon nanostructures have been known and fabricated for more than a hundred years and were originally On-chip decoupling capacitor of specific capacitance 55 pF/μm2 (footprint area) which is 10 times higher than the commercially available discrete and on-chip (65 nm technology node) decoupling capacitors is presented. The electrodes of the capacitor are based on vertically aligned carbon nanofibers (CNFs) capable of being integrated directly on CMOS chips. The carbon nanofibers employed in this study were grown on CMOS chips using direct current plasma enhanced chemical vapor deposition (DC-PECVD) technique at CMOS compatible temperature. The carbon nanofibers were grown at temperature from 390 °C to 550 °C. The capacitance of the carbon nanofibers was measured by cyclic voltammetry and thus compared. Futhermore the capacitance of decoupling capacitor was measured using different voltage scan rate to show their high charge storage capability and finally the cyclic voltammetry is run for 1,000 cycles to assess their suitability as electrode material for decoupling capacitor. Our results show the high specific capacitance and long-term reliability of performance of the on-chip decoupling capacitors. Moreover, the specific capacitance shown is larger for carbon nanofibers grown at higher temperature.
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