New method accelerates CNF-MIM development

While seek­ing buy­ers for our CNF-MIM tech­no­logy, we con­tin­ue to refine our offer­ings. Recently, we’ve made sig­ni­fic­ant pro­gress by trip­ling the capa­cit­ance dens­ity of our CNF-MIM capa­cit­ors while halv­ing the leak­age cur­rent with a new dielec­tric stack.

To put this in per­spect­ive for non-experts, increased capa­cit­ance dens­ity means a great­er abil­ity to store energy in the form of elec­tric charge with­in the same volume. Sim­il­arly, reduced leak­age cur­rent means that the loss of stored energy is reduced, mak­ing our capa­cit­ors more efficient.

Such advance­ments boost the appeal of our tech­no­logy to poten­tial buy­ers. How­ever, break­throughs require extens­ive exper­i­ment­a­tion. To min­im­ize time-to-mar­ket, we need rap­id exper­i­ment setup cap­ab­il­it­ies. Man­u­fac­tur­ing full CNF-MIM capa­cit­ors is time-con­sum­ing and costly. For quick­er turn­around, we use par­al­lel plate capa­cit­ors – sim­pler and cheap­er to pro­duce. Now, Smol­tek Semi research­ers have fur­ther accel­er­ated and eco­nom­ized this process.

Parallel plate capacitors as proxies

A par­al­lel plate capa­cit­or is the simplest form of capa­cit­or: two met­al plates sep­ar­ated by an insu­lat­or. CNF-MIM capa­cit­ors share this basic struc­ture, but add car­bon nan­ofibers to increase the met­al sur­face area many times over. Both types con­sist of par­al­lel met­al sur­faces sep­ar­ated by a dielec­tric stack of uni­form thickness.

We man­u­fac­ture par­al­lel plate capa­cit­ors using the same meth­ods and mater­i­als as CNF-MIM capa­cit­ors, includ­ing cre­at­ing them on a sil­ic­on wafer sub­strate. The only dif­fer­ence is that we omit the car­bon nan­ofiber steps for par­al­lel plate capa­cit­ors. This sim­il­ar­ity in pro­duc­tion meth­ods, minus the nan­ofibers, makes par­al­lel plate capa­cit­ors excel­lent sub­sti­tutes for test­ing CNF-MIM tech­no­logy, as they mim­ic CNF-MIM capa­cit­ors while being sim­pler and quick­er to produce.

Simplifying electrode access

Con­nect­ing a capa­cit­or requires access to both met­al plates, each of which is called an elec­trode in this con­text. The top elec­trode is eas­ily access­ible, but the bot­tom elec­trode poses chal­lenges. It’s covered by the top elec­trode and the dielec­tric stack, and can’t be accessed from below due to the substrate.

Pre­vi­ously, cre­at­ing an elec­tric­al con­nec­tion to the bot­tom elec­trode required sev­er­al com­plex steps. Now, Smol­tek Semi research­ers use a meth­od we call ”zap­ping” that sig­ni­fic­antly sim­pli­fies this pro­cess. While not a nov­el tech­nique in itself, it’s new for us to apply it in this con­text. The zap­ping meth­od involves apply­ing a brief, high voltage across spe­cif­ic con­tact points on a test capa­cit­or, cre­at­ing a con­trolled break­down in the insu­lat­ing lay­er. This tech­nique elim­in­ates the need for mul­tiple com­plex etch­ing steps, sig­ni­fic­antly stream­lin­ing the test­ing process.

For those unfa­mil­i­ar with elec­tric­al engin­eer­ing, ima­gine try­ing to con­nect a wire to the bot­tom of a stack of sand­wiches without dis­turb­ing the top lay­ers. The old meth­od was like care­fully cut­ting through each lay­er to reach the bot­tom. The new zap­ping meth­od is more like using a focused beam of energy to instantly melt a tiny, pre­cise hole through the lay­ers. This approach is much faster and causes min­im­al dis­rup­tion to the over­all struc­ture, as it affects only a very small, con­trolled area.

It’s worth not­ing that zap­ping is a devel­op­ment tool that sim­pli­fies CNF-MIM capa­cit­or char­ac­ter­iz­a­tion. It’s not inten­ded for actu­al capa­cit­or production.

Why zapping matters

Zap­ping reduces sev­er­al fab­ric­a­tion steps for test capa­cit­ors, short­en­ing iter­a­tion time from a month to a week. This accel­er­a­tion allows more fre­quent test­ing of new con­fig­ur­a­tions, speed­ing up research and optim­iz­a­tion. It enables rap­id eval­u­ation of mater­i­als and design para­met­ers, focus­ing efforts on crit­ic­al com­pon­ents like the dielec­tric stack without lengthy pro­duc­tion cycles.

Business impact

Zap­ping enhances Smoltek’s pos­i­tion by mak­ing devel­op­ment more cost-effi­cient and rap­id. It reduces R&D expenses, allow­ing more exper­i­ments and tech­no­logy refine­ment without over­spend­ing. This accel­er­ated pace enables quick­er deliv­ery of pre­lim­in­ary res­ults to poten­tial part­ners, main­tain­ing their engage­ment and interest.

In nego­ti­ations, demon­strat­ing high-per­form­ing, cost-effect­ive tech­no­logy devel­op­ment makes Smol­tek a more attract­ive part­ner. While zap­ping isn’t used in final pro­duc­tion, the abil­ity to iter­ate quickly ensures a reli­able, scal­able end product – key con­sid­er­a­tions for poten­tial cus­tom­ers seek­ing eas­ily integ­rated solutions.

Investor perspective

For share­hold­ers, zap­ping trans­lates into a clear advant­age: faster devel­op­ment cycles mean a short­er time-to-mar­ket for break­throughs, such as trip­ling the capa­cit­ance dens­ity and halv­ing the leak­age cur­rent, mak­ing CNF-MIM capa­cit­ors even more attract­ive to buyers.

Accelerating smart development

Zap­ping sig­ni­fic­antly reduces devel­op­ment time and costs, enabling faster iter­a­tion and main­tain­ing our com­mer­cial­iz­a­tion tra­ject­ory. It’s a prag­mat­ic approach that bol­sters our mar­ket pos­i­tion and enhances our appeal to poten­tial buyers.